CD74HC4075PWR >
CD74HC4075PWR
Texas Instruments
IC GATE OR 3CH 3-INP 14TSSOP
3695 Pcs New Original In Stock
OR Gate IC 3 Channel 14-TSSOP
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CD74HC4075PWR Texas Instruments
5.0 / 5.0 - (169 Ratings)

CD74HC4075PWR

Product Overview

1261930

DiGi Electronics Part Number

CD74HC4075PWR-DG

Manufacturer

Texas Instruments
CD74HC4075PWR

Description

IC GATE OR 3CH 3-INP 14TSSOP

Inventory

3695 Pcs New Original In Stock
OR Gate IC 3 Channel 14-TSSOP
CAD Models - PCB Symbols & Footprints
Quantity
Minimum 1

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In Stock (All prices are in USD)
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  • 1 0.1730 0.1730
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CD74HC4075PWR Technical Specifications

Category Logic, Gates and Inverters

Manufacturer Texas Instruments

Packaging Cut Tape (CT) & Digi-Reel®

Series 74HC

Product Status Active

Logic Type OR Gate

Number of Circuits 3

Number of Inputs 3

Features -

Voltage - Supply 2V ~ 6V

Current - Quiescent (Max) 2 µA

Current - Output High, Low 5.2mA, 5.2mA

Input Logic Level - Low 0.5V ~ 1.8V

Input Logic Level - High 1.5V ~ 4.2V

Max Propagation Delay @ V, Max CL 17ns @ 6V, 50pF

Operating Temperature -55°C ~ 125°C

Mounting Type Surface Mount

Supplier Device Package 14-TSSOP

Package / Case 14-TSSOP (0.173", 4.40mm Width)

Base Product Number 74HC4075

Datasheet & Documents

HTML Datasheet

CD74HC4075PWR-DG

Environmental & Export Classification

RoHS Status ROHS3 Compliant
Moisture Sensitivity Level (MSL) 1 (Unlimited)
REACH Status REACH Unaffected
ECCN EAR99
HTSUS 8542.39.0001

Additional Information

Other Names
-296-9228-1-DG
CD74HC4075PWRE4-DG
296-9228-1
CD74HC4075PWRG4-DG
296-9228-2
296-9228-2-NDR
-CD74HC4075PWRE4
-CD74HC4075PWRE4-NDR
-CD74HC4075PWRG4
296-9228-6
-296-9228-1
CD74HC4075PWRE4
-CD74HC4075PWR-NDR
CD74HC4075PWRG4
TEXTISCD74HC4075PWR
-CD74HC4075PWRG4-NDR
2156-CD74HC4075PWR
296-9228-1-NDR
Standard Package
2,000

Alternative Parts

PART NUMBER
MANUFACTURER
QUANTITY AVAILABLE
DiGi PART NUMBER
UNIT PRICE
SUBSTITUTE TYPE
74HC4075PW-Q100J
Nexperia USA Inc.
3022
74HC4075PW-Q100J-DG
0.0017
Similar
74HCT4075PW,118
Nexperia USA Inc.
731
74HCT4075PW,118-DG
0.0017
Direct
CD74HC4075PWT
Texas Instruments
4027
CD74HC4075PWT-DG
0.0017
Parametric Equivalent
CD74HC4075PW
Texas Instruments
1480
CD74HC4075PW-DG
0.0017
Direct
74HCT4075DB,118
Nexperia USA Inc.
1131
74HCT4075DB,118-DG
0.0017
Similar

Reviews

5.0/5.0-(Show up to 5 Ratings)
달***다
Dec 02, 2025
5.0
처음인데도 매우 빠른 배송과 안전한 포장이 인상적이었어요.
Source***umière
Dec 02, 2025
5.0
Je suis très satisfait de la politique de prix de Di Digi Electronics, très avantageuse pour les achats en gros.
陽***空
Dec 02, 2025
5.0
価格もお手頃で、環境に配慮されたパッケージに共感します。
Infi***eHope
Dec 02, 2025
5.0
Speedy dispatch meant I could enjoy my product sooner than expected.
Tr***ibe
Dec 02, 2025
5.0
Their inventory management system is top-notch, minimizing our procurement hassle.
War***ves
Dec 02, 2025
5.0
DiGi Electronics' customer support is always responsive and knowledgeable—they truly understand DIYer needs.
Gold***orge
Dec 02, 2025
5.0
Their prices make quality technology attainable for a wide audience.
Hope***loom
Dec 02, 2025
5.0
Working with DiGi Electronics gives us peace of mind knowing support is always available.
Bri***Echo
Dec 02, 2025
5.0
DiGi Electronics consistently delivers reliable products that meet high quality standards.
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Frequently Asked Questions (FAQ)

I’m squeezing CD74HC4075PWR into a 1.8 V FPGA interface; will the 1.5 V VIH threshold leave me enough noise-margin at 125 °C, and what layout tricks buy me the extra 200 mV?

CD74HC4075PWR keeps VIH ≤ 1.5 V (at 2 V supply) only when TA ≤ 25 °C; at 125 °C the knee drifts up to ~1.8 V because of internal VT drop. Running the gate on the minimum 2 V rail therefore leaves you zero margin. Raise VCC to 3.0–3.3 V (still within the 6 V abs-max) so VIH stays 1.5 V max, then insert a 220 Ω series damping resistor at each input to cut ground-bounce; keep trace length <25 mm and add a 100 pF chip cap to GND within 5 mm of the pin. This gives 0.7 V hysteresis at 125 °C while adding only 0.8 ns to the 17 ns tpd budget.

Can I drop CD74HC4075PWR straight onto a SN74HC4075N DIP footprint for a field retro-fit, or do the extra latches in the TSSOP pkg change the flow-through delay?

CD74HC4075PWR is function-pin-compatible with SN74HC4075N, but the TSSOP body shrinks pad pitch to 0.65 mm vs. 2.54 mm DIP. Use an SMT-to-DIP adapter board (44 mm long) and keep total CL <15 pF if your original board ran at 5 V with ~25 ns traces; the HC family die is identical, so propagation stays 17 ns typical @ 5 V, 50 pF. Add a 20 Ω series resistor on each adapter trace to mimic the DIP lead inductance and avoid overshoot on long 1980-era backplanes.

I need to parallel two channels of CD74HC4075PWR to boost 5 V bus-drive to 10 mA; any thermal or shoot-through risk when the outputs inadvertently skew 2 ns?

CD74HC4075PWR outputs are push-pull and will contend if they disagree. With 5.2 mA per stage, a 2 ns skew at 40 MHz creates ~65 pC charge mismatch that momentarily draws 400 mA. Add a 47 Ω shared resistor on the merged node so the voltage difference never exceeds 0.5 V, keeping current <10 mA and holding junction temp rise <2 °C. This preserves reliability while giving you a combined 8 mA source/sink capability—enough for a 50 Ω back-termination.

Running CD74HC4075PWR from a 6 V Li-ion (max 6.3 V) for legacy TTL compatibility—how far can the supply overshoot before reliability creeps suffer, and what de-rating capacitor value keeps dV/dt safe during hot-plug?

CD74HC4075PWR is guaranteed for 6.5 V abs-max, but at 6.3 V you’re only 200 mV from the HC process wear-out knee. Add a 5.6 V 500 mW zener (BZX79-C5V6) in shunt with a 10 µF X7R + 100 nF ceramic; the low ESR stack clamps hot-plug overshoot to 5.9 V and holds dV/dt <0.5 V/µs, ensuring MTBF >200 khr at 85 °C. Limit continuous 6 V duty to <50 % of system life to prevent gate oxide drift.

Will CD74HC4075PWR meet 1 kV HBM ESD on a handheld sensor, or should I swap in Nexperia 74HCT4075BQ to avoid external TVS diodes?

CD74HC4075PWR is standard 2 kV HBM, adequate for controlled assembly but marginal for user-exposed pins. Nexperia 74HCT4075BQ offers the same footprint and 2 kV rating—no gain. Instead, add dual 0402 SP72xx 24 V TVS arrays on each input; they add 0.8 pF, keeping total CL <7 pF, well under the 50 pF spec, while pushing system ESD to 8 kV contact and 15 kV air. Cost is <$0.04 vs. a reel-requal, and you stay with TI’s wider -55 °C ~ 125 °C temp range.

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